Cache memory structures are used in computer systems by devices, such as central processing units (CPUs), graphical processing units (GPUs), etc. to reduce the average latency and/or reduce the bandwidth needs to main memory. Cache memory structures are commonly designed to provide a certain associativity, meaning that there are multiple alternate locations where a specific cache line may be placed. The associativity implies that multiple locations need to be searched when doing a cache tag look-up. In general, for an N-way associative cache, each look-up involves examining N tags. Each examination of the tags typically involves processing the tags in parallel by reading out the tag from a static random access memory (SRAM) and comparing it to the requested address. For highly associative caches, the processing power used for parallel look-ups may result in a significant energy use cost.